Low drop-out (LDO) voltage regulators are implemented in a variety of circuit applications to provide regulated power supplies. Increased regulator performance is especially being demanded in mobile battery-operated products such as cellular phones, pagers, camcorders, and laptop computers. For these products, regulators having a high power supply rejection ratio (PSRR) to yield low noise and ripple are needed. Regulators of this type are preferentially fabricated in standard low-cost CMOS processes, making them difficult to realize with the required performance characteristics.
A journal publication entitled “A Low-Noise High PSRR, Low Quiescent Current, Low Drop-out Regulator” by Hafid Amrani et al. states that regulators with high PSRR require a first stage amplifier with a large gain-bandwidth product. The gain-bandwidth product of an amplifier is the product of the amplifier's dc gain and its cutoff frequency, which for LDO applications is typically 1 MHz or lower. The required first stage amplifier performance can be achieved by a large dc gain, or by a high cutoff frequency.
A first journal publication entitled “A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator” by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using a current efficient buffer and a current boosted pass device to realize a low quiescent current LDO regulator for low voltage operation.
A second journal publication entitled “Optimized Frequency Shaping Circuit Topologies for LDOS” by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using pole-zero doublet generation to increase the bandwidth for dynamic load regulation.
A third journal publication entitled “Active Capacitor Multiplier in Miller-Compensated Circuits” by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using Miller capacitor multipliers to reduce the silicon area consumed by a voltage regulator.
The main drawbacks of these proposed methods are:
1. The current efficient buffer circuit requires NPN bipolar transistors to avoid creation of a parasitic pole at the output of an error amplifier within the circuit.
2. The structure based on the pole-zero doublet can be stabilized if the dc open-loop gain is relatively small (e.g., 50 dB for a high current load). However, since the dc value of the PSRR is proportional to the inverse of the open-loop gain of the regulator, the dc value of the PSRR for this design cannot exceed 50 dB.
3. The Miller compensation method creates an internal pole. To make the cutoff frequency of the PSRR as high as possible, the pole of the first stage has to be as high as possible. Thus, the PSRR performance of this circuit structure is compromised. The noise performance of the regulator is also reduced.
With reference to FIG. 1, a low drop-out (LDO) regulator circuit 100 as known in the prior art comprises a first amplifier stage 110 and a second amplifier stage 120. The first amplifier stage 110 includes PMOS transistors P112, P116, and P118, diode-connected NMOS transistor N116 and NMOS transistor N118. The second amplifier stage 120 includes diode-connected PMOS transistors P122 and P126, PMOS transistor P124, diode-connected NMOS transistor N124 and NMOS transistors N122 and N126. The second amplifier stage 120 further includes PMOS power transistor P128. Resistive divider circuit comprising a resistor R1 and a resistor R2 is coupled to an output controlled voltage node VOUT. The ratio of the resistor R1 to the resistor R2 controls a proportion of the potential on the output controlled voltage node VOUT which is fed back to the first amplifier stage. By varying the resistor R1 and the resistor R2, the output voltage of the regulator circuit 100 can be programmed. A current load IL is coupled to the output controlled voltage node VOUT, representing an electrical load being powered by the regulator circuit 100 and requiring a consistent operating voltage. An external decoupling capacitance CL with an associated equivalent series resistance (ESR) RS is connected in parallel with the current load IL. Skilled artisans will recognize that a plurality of applications exist, such as the operation of microprocessor circuits, mixed signal circuits, memory circuits, and others, which can replace the generic current load IL attached to the regulator circuit 100 in practical use.
An analysis of the regulator circuit 100 operation now follows the assumptions and methods in the cited journal publications. A low-valued equivalent series resistance (ESR) RS is assumed for the external decoupling capacitance CL, which improves the transient ripple of the regulator. A zero introduced by the external decoupling capacitance CL and the equivalent series resistance (ESR) RS into the system transfer function is therefore at a higher frequency than the unity gain frequency (UGF) of the open-loop, and does not alter the stability of the regulator circuit 100.
As described in the journal article by Hafid Amrani et al., a dominant pole p1 of the regulator response is determined by the external decoupling capacitance CL as:
                              p          1                =                                            gd                              P                ⁢                                                                  ⁢                128                                      +                          (                              1                                                      R                    ⁢                                                                                  ⁢                    1                                    +                                      R                    ⁢                                                                                  ⁢                    2                                                              )                                            2            ⁢            Π            ⁢                                                  ⁢                          C              L                                                          (        1        )            
In formula (1), gdP128 represents the output admittance of PMOS power transistor P128. The output admittance gdP128 can be expressed as a function of the current load IL and a channel modulation parameter, λ, of PMOS power transistor P128:gdP128=λ*IL  (2)
For a current load IL that is much larger than
      (                  1                  R          ⁢                                          ⁢          1          *          R          ⁢                                          ⁢          2                    *              1        λ              )    ,the pole frequency can be approximated as:
                              p          1                ≈                              λ            *                          I              L                                            2            ⁢            Π            ⁢                                                  ⁢                          C              L                                                          (        3        )            
For a typical CMOS process, λ is of the order of 0.1 V−1 and typical low-noise regulator applications employ a resistive divider such that (R1+R2) is of the order of 100 kΩ. Under these conditions, formula (3) is valid for load currents which are large in comparison with approximately 100 μA. Thus, for a current load IL of 1 mA or more, the dominant pole of the open-loop transfer function increases with increasing current.
The dc gain, GDC, of the open-loop transfer function of the regulator circuit 100 can be expressed as:
                                                                        G                DC                            =                                                                    gm                                          P                      ⁢                                                                                          ⁢                      118                                                                                                  gd                                              P                        ⁢                                                                                                  ⁢                        118                                                              +                                          gd                                              N                        ⁢                                                                                                  ⁢                        118                                                                                            *                                                                            k                      1                                        *                                          k                      2                                                        a                                *                                                      gm                                          N                      ⁢                                                                                          ⁢                      122                                                                                                  gd                                              P                        ⁢                                                                                                  ⁢                        128                                                              +                                          1                                                                        R                          ⁢                                                                                                          ⁢                          1                                                +                                                  R                          ⁢                                                                                                          ⁢                          2                                                                                                                    *                                                      R                    ⁢                                                                                  ⁢                    2                                                                              R                      ⁢                                                                                          ⁢                      1                                        +                                          R                      ⁢                                                                                          ⁢                      2                                                                                                                                              with              ⁢                              :                                                                        (        4        )                                          gm                      N            ⁢                                                  ⁢            122                          =                              2            *                          K              n                        *                                                            I                  L                                *                a                                                              k                  1                                *                                  k                  2                                                      *                                          W                                  N                  ⁢                                                                          ⁢                  122                                                            L                                  N                  ⁢                                                                          ⁢                  122                                                                                        (        5        )            
In formulae (4) and (5), gm represents the transconductance of the associated subscripted transistor name, e.g., gmP118 represents the transconductance of PMOS transistor P118. Analogously, gd represents the output admittance of the associated subscripted transistor name, e.g., gdP118 represents the output admittance of PMOS transistor P118. The parameters k1 and k2 represent width ratios of current mirror transistors, such that k1=WP124/WP122 and k2=WN126/WN124, where W indicates the channel width of the associated subscripted transistor name.
The variable L in formula (5) represents the channel length of the associated subscripted transistor name, i.e., LN122 is the channel length of the NMOS transistor N122. The parameter Kn in formula (5) is the transconductance parameter for the NMOS transistors, and can be further represented as Kn=μn*Cox, where μn is the carrier mobility for electrons and Cox is the capacitance per unit area of the gate oxide. The parameter α is a fraction of the current load IL flowing in PMOS transistor P126. It is also equal to a width ratio of the diode-connected PMOS transistor P126 and the PMOS power transistor P128. Both the diode-connected PMOS transistor P126 and the PMOS power transistor P128 are designed with the same channel length to facilitate current matching, i.e., LP126=LP128 and α=WP126/WP128.
Using the approximation given by formula (3), and combining formulae (2) and (5) into (4) gives GDC as a decreasing function of IL:
                              G          DC                =                                            gm                              P                ⁢                                                                  ⁢                118                                                                    gd                                  P                  ⁢                                                                          ⁢                  118                                            +                              gd                                  N                  ⁢                                                                          ⁢                  118                                                              *                                                    2                *                Kn                *                                                                            k                      1                                        *                                          k                      2                                                        a                                            λ                                *                                    R              ⁢                                                          ⁢              2                                                      R                ⁢                                                                  ⁢                1                            +                              R                ⁢                                                                  ⁢                2                                              *                      1                                          I                L                                                                        (        6        )            
A second pole p2 is introduced into the regulator open-loop response as a result of the large output impedance of the first amplifier stage 110 and an input capacitance CN122, associated with the second amplifier stage 120. The second pole p2 value can be expressed as:
                              p          2                =                                            gd                              P                ⁢                                                                  ⁢                118                                      +                          gd                              N                ⁢                                                                  ⁢                118                                                          2            ⁢            Π            ⁢                                                  ⁢                          C                              N                ⁢                                                                  ⁢                122                                                                        (        7        )            
The capacitance CN122 is determined by the gate-to-source capacitance and Miller gate-to-drain capacitance of the NMOS transistor N122 according to:
                              C                      N            ⁢                                                  ⁢            122                          =                                                                              Cgs                                      N                    ⁢                                                                                  ⁢                    122                                                  +                                                      Cgd                                          N                      ⁢                                                                                          ⁢                      122                                                        *                                                                                                                                                                    k                      ⁢                                                                                          ⁢                      1                      *                      k                      ⁢                                                                                          ⁢                      2                                        a                                    *                                                            K                      n                                                              K                      p                                                        *                                                            W                                              N                        ⁢                                                                                                  ⁢                        122                                                                                    W                                              P                        ⁢                                                                                                  ⁢                        128                                                                              *                                                            L                                              P                        ⁢                                                                                                  ⁢                        128                                                                                    L                                              N                        ⁢                                                                                                  ⁢                        122                                                                                                                                                    (        8        )            
In formula (8) Kp=μp*Cox is the transconductance parameter for PMOS transistors, μp is the carrier mobility for holes, and Cox is the capacitance per unit area of the gate oxide. CgsN122 is the gate-to-source capacitance for NMOS transistor N122 and CgdN122 is the gate-to-drain capacitance for NMOS transistor N122.
Formula (8) shows that CN122, and thus p2, are not a function of current load IL, whereas the dominant pole p1 and the dc gain GDC depend upon IL. In standard CMOS processes, pole p2 is typically at a frequency lower than 100 kHz, and therefore below the unity gain frequency. This makes the system transfer function second order and unstable. As previously mentioned, and discussed in the journal article by Hafid Amrani et al., to maintain adequate power supply rejection ratio (PSRR) performance, the regulator circuit 100 configures the first amplifier stage 110 with high dc gain. For maximum stability, the pole P2 is preferably as high in frequency as possible. The approach employed in the regulator circuit 100 is to add a zero in the feedback loop to stabilize the system. The zero is implemented by means of zero stabilizing resistor R115 and zero stabilizing capacitor C115 at the output of the first amplifier stage 110. The resistor R115 and the capacitor C115 series configuration create a pole-zero doublet (pc, zc) in the open-loop transfer function. The zero zc is placed after the unity gain frequency (UGF) such that the open-loop gain crosses the 0 dB axis with a −20 dB per decade slope. The zero stabilizing capacitor C115 is chosen to have a low value to reduce the frequency of the pole p2 of the first amplifier stage 110 according to:
                              p          ⁢                                          ⁢          2                =                              1                          2              ⁢              Π                                *                      1                                                                                C                                          N                      ⁢                                                                                          ⁢                      122                                                        +                                      C                    ⁢                                                                                  ⁢                    115                                                                                        gd                                          P                      ⁢                                                                                          ⁢                      118                                                        +                                      gd                                          N                      ⁢                                                                                          ⁢                      118                                                                                  +                              R                ⁢                                                                  ⁢                115                *                C                ⁢                                                                  ⁢                115                                                                        (        9        )            
The pole-zero doublet (pc, zc) can be expressed as:
                    zc        =                  1                      2            ⁢            Π            ⁢                                                  ⁢            C            ⁢                                                  ⁢            115            *            R            ⁢                                                  ⁢            115                                              (        10        )                                pc        =                  zc          ⁡                      (                          1              +                                                                    C                    ⁢                                                                                  ⁢                    115                                                        C                                          N                      ⁢                                                                                          ⁢                      122                                                                      *                                  [                                      1                    +                                                                  (                                                                              gd                                                          P                              ⁢                                                                                                                          ⁢                              118                                                                                +                                                      gd                                                          N                              ⁢                                                                                                                          ⁢                              118                                                                                                      )                                            *                      R                      ⁢                                                                                          ⁢                      115                                                        ]                                                      )                                              (        11        )            
Like pole p2, pc and zc are independent of the current load IL. Comparison of formulae (9), (10), and (11) shows that p2<zc<pc. Therefore, the regulator is stable regardless of the value of the current load IL. The system transfer function becomes locally a first order transfer function.
In addition to the discussions supra, the first journal publication by Gabriel A. Rincon-Mora and Phillip E. Allen explains that a third pole p3 is realized by the gate node of the PMOS output transistor P128. By application of a boost technique described in the first publication, pole p3 can easily be increased in frequency beyond the unity-gain frequency (UGF) of the open-loop system such that pole p3 does not alter system stability. To apply the boost technique in the regulator circuit 100 a fraction of the current load IL is sourced into the bulk terminal (not shown) of the diode-connected PMOS transistor P126. Typically, the current fraction is between 1/1000 and 1/100. By sourcing current into the bulk terminal of the diode-connected PMOS transistor P126, the threshold voltage of the diode-connected PMOS transistor P126 and the PMOS power transistor P128 is effectively lowered, producing an increase in the conductance of PMOS power transistor P128 and an increase in the associated pole p3 frequency. Additionally, the current mirrors of ratio k1 and k2 are implemented to reduce the current in the NMOS transistor N122. Reduction of the current in the NMOS transistor N122 enables the W/L ratio WN122/LN122 to be reduced, thereby reducing the CN122 capacitance. Reference to formula (7), supra, shows that reduction in the CN122 capacitance raises the pole p2 frequency. The higher pole p2 frequency enables zc to be increased in frequency, permitting a reduction in zero stabilizing resistor R115 and zero stabilizing capacitor C115 values.
The architecture of the regulator circuit 100 results in the gate node of PMOS power transistor P128 acting as a low impedance net due to the action of the diode-connected PMOS transistor P126 according to the relation:
                              gm                      P            ⁢                                                  ⁢            126                          =                  a          *                                    2              *              Kp              *                              I                L                            *                                                W                                      P                    ⁢                                                                                  ⁢                    128                                                                    L                                      P                    ⁢                                                                                  ⁢                    128                                                                                                          (        12        )            
The boost technique consists of increasing α, thereby increasing gmP126. The third pole value can be expressed as a function of current load IL:
                              p          ⁢                                          ⁢          3                =                              1                          2              ⁢              Π                                *          a          *                                                    2                *                Kp                *                                                      W                                          P                      ⁢                                                                                          ⁢                      128                                                                            L                                          P                      ⁢                                                                                          ⁢                      128                                                                                                                                                      ⁢                                                Cgs                                      P                    ⁢                                                                                  ⁢                    128                                                  +                                  Cgd                                      P                    ⁢                                                                                  ⁢                    128                                                                                *                                    I              L                                                          (        13        )            
In formula (13), CgsP128 is the gate-to-source capacitance of PMOS power transistor P128 and CgdP128 is the gate-to-drain capacitance of the PMOS power transistor P128.
The PMOS power transistor P128 operates in the saturation region, so the following relations apply:
                              Cgs                      P            ⁢                                                  ⁢            128                          =                              2            3                    *          Cox          *                      W                          P              ⁢                                                          ⁢              128                                *                      L                          P              ⁢                                                          ⁢              128                                                          (                  14          ⁢                                          ⁢          A                )                                          Cgd                      P            ⁢                                                  ⁢            128                          =                              1            3                    *          Cox          *                      W                          P              ⁢                                                          ⁢              128                                *                      L                          P              ⁢                                                          ⁢              128                                                          (                  14          ⁢          B                )            
Applying formulae (14A) and (14B) to formula (13) gives:
                              p          ⁢                                          ⁢          3                =                              1                          2              ⁢              Π                                *                      a                          Cox              *                              L                                  P                  ⁢                                                                          ⁢                  128                                                              *                                                    2                *                Kp                                                              W                                      P                    ⁢                                                                                  ⁢                    128                                                  +                                  L                                      P                    ⁢                                                                                  ⁢                    128                                                                                *                                    I              L                                                          (        15        )            
Formula (15) shows that the third pole p3 is an increasing function of the current load IL. The current ratio α is preferentially large enough to ensure p3 is higher than the unity-gain frequency (UGF) of the open-loop, so that p3 does not alter the regulator stability. Increasing the current ratio a requires a compromise between the phase margin and the current efficiency performance of the regulator circuit 100.
To recapitulate the analysis, supra, transfer function pole p2, zero zc, and pole pc have been shown to be independent of IL by formulae (9), (10) , and (11) respectively. However, the dc gain GDC is a function of
  1            I      L      as shown by formula (6), and the dominant pole p1 is a function of IL as shown by formula (3). The unity gain frequency (UGF) of the open-loop varies with a factor of √{square root over (IL)} as:
                    UGF        =                              (                                          G                DC                            *              p              ⁢                                                          ⁢              1                        )                    ⁢                      (                                          p                ⁢                                                                  ⁢                2                            zc                        )                                              (        16        )            
Formula 16 implicitly shows that the unity gain frequency (UGF) and hence the regulator stability, depends on the current load IL. It becomes difficult to maintain stability when large variations in current load IL are desired.
What is needed, therefore, is a method of realizing a high performance regulator which takes advantage of CMOS fabrication processes in order to provide low noise, stable operation, and low-ripple voltage regulation without requiring tradeoffs between current efficiency and stability.